Magnetoresistive memory cell array and mram memory comprising such array

ABSTRACT

The present invention describes a matrix with magnetoresistive memory cells arranged in logically organized rows and columns, Each memory cell includes a magnetoresistive element. The matrix comprises means for simultaneously reading from one cell in a column and writing to another cell in a column, or means for simultaneous reading from one cell in a row and writing to another cell in the same row. Such matrix can be used in a read-while-write MRAM memory.

The present invention relates to a matrix of magnetoresistive memorycells and to non-volatile magnetic memories, more particularly tomagnetoresistive random access memories (MRAMs), comprising such amatrix and methods of operating the same.

Magnetic or Magnetoresistive Random Access Memory (MRAM) is currentlybeing considered by many companies as a successor to flash memory. Ithas the potential to replace all but the fastest static RAM (SRAM)memories. It is a non-volatile memory device, which means that no poweris required to sustain the stored information. This is seen as anadvantage over most other types of memory.

The MRAM concept was originally developed at Honeywell Corp. USA, anduses magnetization direction in a magnetic multilayer device asinformation storage and the resultant resistance difference forinformation readout. As with all memory devices, each cell in an MRAMarray must be able to store at least two states which represent either a“1” or a “0”.

Different kinds of magnetoresistive (MR) effects exist, of which theGiant Magneto-Resistance (GMR) and Tunnel Magneto-Resistance (TMR) arecurrently the most important ones. The GMR effect and the TMR orMagnetic Tunnel Junction (MTJ) or Spin Dependent Tunneling (SDT) effectprovide possibilities to realize a.o. non-volatile magnetic memories.These devices comprise a stack of thin films of which at least two areferromagnetic or ferrimagnetic, and which are separated by anon-magnetic interlayer. GMR is the magneto-resistance for structureswith conductor interlayers and TMR is the magneto-resistance forstructures with dielectric interlayers. If a very thin conductor isplaced between two ferromagnetic or ferrimagnetic films, then theeffective in-plane resistance of the composite multilayer structure issmallest when the magnetization directions of the films are parallel andlargest when the magnetization directions of the films areanti-parallel. If a thin dielectric interlayer is placed between twoferromagnetic or ferrimagnetic films, tunneling current between thefilms is observed to be the largest (or thus resistance to be thesmallest) when the magnetization directions of the films are paralleland tunneling current between the films is the smallest (or thusresistance the largest) when the magnetization directions of the filmsare anti-parallel.

Magneto-resistance is usually measured as the percentage increase inresistance of the above structures going from parallel to anti-parallelmagnetization states. TMR devices provide higher percentagemagneto-resistance than GMR structures, and thus have the potential forhigher signals and higher speed. Recent results indicate tunnelinggiving over 40% magneto-resistance, compared to 6-9% magneto-resistancein good GMR cells.

A magnetic tunnel junction magnetoresistive random access memory (MTJMRAM) comprises a plurality of magnetoresistive memory cells 1 arrangedin an array. One such prior art memory cell 1 is shown in FIG. 1. Eachmemory cell 1 comprises a magnetoresistive memory element 2, a firstintersection of a digit line 4 and a bit line 6, and a secondintersection of the bit line 6 and a word line 8. The memory cells 1 arecoupled in series in columns by means of the bit lines 6 and coupled inseries in rows by means of the digit lines 4 and word lines 8, thusforming the array. The magnetoresistive memory elements 2 used aremagnetic tunnel junctions (MTJs).

MTJ memory elements 2 generally include a non-magnetic conductor forminga lower electrical contact, a pinned magnetic layer, a dielectricbarrier layer positioned on the pinned layer, and a free magnetic layerpositioned on the dielectric barrier layer, with an upper contact on thefree magnetic layer. The pinned magnetic layer and the free magneticlayer may both be composed of e.g. NiFe, and the dielectric barrierlayer may e.g. be made of AlOx.

The pinned layer of magnetic material has a magnetic vector that alwayspoints in the same direction. The magnetic vector of the free layer isfree, but constrained by the physical size of the layer, to point ineither of two directions: parallel or anti-parallel with themagnetization direction of the pinned layer.

An MTJ memory element 2 is used by connecting it in a circuit such thatelectricity can flow vertically through the element 2 from one of themagnetic layers to the other. The MTJ cell 1 can be electricallyrepresented by a resistor R in series with a switching element such as atransistor T, as shown in FIG. 1. The size of the resistance of theresistor R depends on the orientation of the magnetic vectors of thefree and pinned magnetic layers of the memory element 2. The MTJ element2 has a relatively high resistance (HiRes) when the magnetic vectorspoint in opposite directions, and it has a relatively low resistance(LoRes) when the magnetic vectors point in the same direction.

Cross-section and top views of an MTJ cell 1 according to the prior artare shown in FIG. 2, and a diagrammatic elevational view of a 2×2 arrayof prior art cells is shown in FIG. 3. In an MRAM array, comprising aplurality of MRAM cells, orthogonal conductive lines 4, 6 pass under andover each bit or memory element 2, carrying current that produces theswitching field. Each bit is designed so that it will not switch whencurrent is applied to just one line, but will switch when current isflowing through both lines that cross at the selected bit (switchingwill occur only if the magnetic vector of the free layer is not inaccordance with the direction of the switching field).

Digit lines 4 and bit lines 6 are provided in an array of MTJ memorycells 1, where the digit lines 4 travel along the rows of the array onone side of the memory elements 2, and the bit lines 6 travel down thecolumns of the array on the opposite side of the memory elements 2. Thestructure in FIG. 3 is partially inverted for clarity purposes: digitlines 4 physically run underneath the MTJ elements 2 (at that side ofthe MTJ elements 2 oriented towards the substrate in which thetransistor T is provided), and bit lines 6 physically run over the MTJelements 2 (at that side of the MTJ elements 2 oriented away from thesubstrate in which the transistor T is provided). However, if drawn thatway, the bit lines 6 would obscure the magnetoresistive elements 2,which are the more relevant parts of the drawing.

Each memory element 2 is a layered structure comprising a fixed orpinned layer 10, a free layer 12 and a dielectric barrier 14 in between.By applying a small voltage over the sandwich of ferromagnetic orferrimagnetic layers 10, 12 with the dielectric 14 therebetween,electrons can tunnel through the dielectric barrier 14.

The memory element 2 is connected to the transistor T by means of aninterconnect layer 16 and a plurality of metalization layers 18 and vias20. There is a galvanic connection 22 between the memory element 2 andthe bit line 6. The transistor T of each memory cell 1 is connected to aground line 24.

In write or program mode, represented in FIG. 4, required currents flowthrough selected digit lines 4 and bit lines 6 so that at theirintersection a peak magnetic field is generated, sufficient to switchthe polarization of the free layer 12 of the MTJ element 2, so as toswitch the resistance of the MTJ cell 2 from the LoRes (low resistance)state to the HiRes (high resistance) state or vice versa (depending onthe direction of the current through the bit line 6). At the same time,the transistor T in the selected memory cell 1 is in the cut-off stateby keeping the voltage on the word line 8 low (0 volt). For example inthe embodiment represented in FIG. 4, the left cell is selected to beprogrammed. The current through the left bit line 6 is common for boththe left cell and all other cells on that column. Current flows throughthe left digit line 4 of the left cell and all other cells on the samerow, but not through the digit line 4 of the cells at the right. Thecurrents in the digit line 4 and bit line 6 are such that together theyprovide a magnetic field able to change the direction of the magneticvector of the free layer of the foreground left hand cell, but thecurrent in either strip by itself is not able to change the storagestate. Therefore only the selected memory cell (the left one in theexample given) is written.

The information stored in a selected memory cell 1 (the left cell in theexample of FIG. 5) is read by comparing its resistance with theresistance of a reference memory cell located along a same word line 8.The MTJ elements 2 in reference memory cells are not programmed, andtheir resistance value always remains at, for example, the minimumlevel. A memory cell 1 is selected by driving the word line 8 of thatcell to V_(DD) and in that way selecting a row and turning on alltransistors. Current is sent through the bit line 6 of the column inwhich the selected cell is located. Since, of the memory cells in thatcolumn, only the transistor associated with a selected MTJ cell 1 isactivated, current can only flow from the selected bit line 6 to theground line 24 through the selected cell 1. Generally, during a readoutoperation of the whole or a part of the memory array, a first bit line 6will be activated, and the word lines 8 will then be sampledsequentially, i.e. for each cell of each row.

In TMR devices, a sense current has to be applied perpendicular to thelayer planes (CPP—current perpendicular to plane) because the electronshave to tunnel through the barrier layer.

It is a disadvantage of the known MRAM memories that it is not possibleto read one memory cell while writing another memory cell on the samerow or column.

It is an object of the present invention to overcome the disadvantage ofthe prior art MRAM memories. It is an object to provide fast MRAMmemories.

The above objectives are accomplished by the devices and method of thepresent invention.

The present invention describes a matrix with magnetoresistive memorycells arranged in logically organized rows and columns, wherein eachmemory cell includes a magnetoresistive element. The matrix furthermorecomprises means for simultaneously reading from one cell in a column andwriting to another cell in a column, or means for simultaneous readingfrom one cell in a row and writing to another cell in the same row.

The means for simultaneously reading and writing in a row or a columnmay comprise a first column line and a second column line for eachcolumn, the first column line being a write bit line and the secondcolumn line being a read bit line. The first column line is then acontinuous conductive strip which is magnetically couplable to themagnetoresistive element of each of the memory cells of the column, andthe second column line is a continuous conductive strip which iselectrically couplable to an electrode of each of the samemagnetoresistive elements of the memory cells of the column to which thefirst column line is magnetically couplable.

Each row may have a digit line and a word line and each cell may have aswitching element for connecting another electrode of themagnetoresistive element to a voltage source. The digit line is acontinuous conductive strip which is magnetically couplable to themagnetoresistive element of each of the memory cells of a row and theword line is a continuous strip electrically connected to each of theswitching elements of a row.

A closest approach distance of the first column line to themagnetoresistive element of a cell may be smaller than a closestapproach distance of the second column line to the same magnetoresistiveelement.

The magnetoresistive elements in the matrix may comprise a magnetictunnel junction (MTJ).

A matrix according to the present invention may be connected toselecting circuitry for selecting a cell to be read and a cell to bewritten, so as to form a read-while-write MRAM memory. The selectingcircuitry may comprise a row select decoder and a column select decoder.

The selecting circuitry may be adapted to provide electrical energy tothe first and second column lines, the digit lines and the word linesfor simultaneous reading of one cell in a column and writing to anothercell in the same column or reading from one cell in a row and writing toanother cell in the same row. A row current source may be connected tothe row select decoder for providing a selected digit line withelectrical energy. A write bit line current source may be connected tothe column select decoder for providing a selected write bit line withelectrical energy.

Furthermore, sense amplifiers connectable to the second column lines maybe provided for sensing current in the second column lines for readingout selected memory cells.

A method of operating a matrix with magnetoresistive memory cellsarranged in logically organized rows and columns, each cell including amagnetoresistive element, is also provided. The method comprisessimultaneously reading from one cell in a column and writing to anothercell in the same column or simultaneously reading from one cell in a rowand writing of another cell in the same row.

The method may furthermore comprise a selecting step for selecting onerow for reading and another row for writing or selecting one column forreading and another column for writing. The selecting step may includeproviding electrical energy to a write bit line which is magneticallycouplable to the magnetoresistive element to be written, to a read bitline which is electrically couplable to a first electrode of themagnetoresistive element to be read, to a digit line which ismagnetically couplable to the memory element to be written and to a wordline which is electrically connected to a switching element forconnecting a second electrode of the magnetoresistive element to be readto a voltage source.

Other features and advantages of the present invention will becomeapparent from the following detailed description, taken in conjunctionwith the accompanying drawings, which illustrate, by way of example, theprinciples of the invention.

FIG. 1 is an electrical representation of an MTJ cell for connection inan array according to the prior art.

FIG. 2 shows a cross-section and a schematic top view of an MTJ cellwith line 6 partly removed according to the prior art.

FIG. 3 is a diagrammatic elevational view of a 2×2 array of MTJ cellsaccording to the prior art.

FIG. 4 illustrates the conventional process of programming an MTJ memorycell.

FIG. 5 illustrates the conventional process of reading an MTJ memorycell.

FIG. 6 is an electrical representation of an MTJ cell for connection inan array according to an embodiment of the present invention.

FIG. 7 shows a cross-section and a partly sectioned top view of an MTJcell according to an embodiment of the present invention.

FIG. 8 shows an electrical representation of a 2×2 matrix of MTJ cellsaccording to an embodiment of the present invention.

FIG. 9 shows a schematic block diagram of the matrix of FIG. 8.

FIG. 10 is a diagrammatic elevational view of the 2×2 matrix of FIG. 8,wherein the magnetoresistive memory elements are MTJ elements.

FIG. 11 shows a simplified block schematic of an MRAM memory accordingto an embodiment of the present invention.

In the different Figs., the same reference numbers refer to the same oranalogous elements.

The present invention will be described with respect to particularembodiments and with reference to certain drawings but the invention isnot limited thereto but only by the claims. The drawings described areonly schematic and are non-limiting. In the drawings, the size of someof the elements may not be drawn on scale for illustrative purposes.Where the term “comprising” is used in the present description andclaims, is does not exclude other elements or steps. Where an indefiniteor definite article is used when referring to a singular noun e.g. “a”or “an”, “the”, this includes a plural of that noun unless somethingelse is specifically stated.

Throughout this description, the terms “column” and “row” are used todescribe sets of array elements which are linked together. The linkingcan be in the form of a Cartesian array of rows and columns however thepresent invention is not limited thereto. As will be understood by thoseskilled in the art, columns and rows can be easily interchanged and itis intended in this disclosure that these terms be interchangeable.Also, non-Cartesian arrays may be constructed and are included withinthe scope of the invention. Accordingly the terms “row” and “column”should be interpreted widely. To facilitate in this wide interpretation,the claims refer to logically organized rows and columns. By this ismeant that sets of memory elements are linked together in atopologically linear intersecting manner however, that the physical ortopographical arrangement need not be so. For example, the rows may becircles and the columns radii of these circles and the circles and radiiare described in this invention as “logically organized” rows andcolumns. Also, specific names of the various lines, e.g. bit line, wordline, digit line, etc. are intended to be generic names used tofacilitate the explanation and to refer to a particular function andthis specific choice of words is not intended to limit the invention.

An MTJ memory cell, which can be used in a memory array according to anembodiment of the present invention, is shown schematically in FIG. 6and in cross-section and in partly sectioned topview in FIG. 7. As canbe seen from these drawings, more particularly from FIG. 6 and from thetop view part of FIG. 7, for one MTJ memory cell 30 according to thepresent invention, two bit lines are provided: a read bit line 32 and awrite bit line 34. The write bit line 34 is not connected, and thus notelectrically couplable, to the MTJ element 2. It is however magneticallycoupled to the MTJ element 2 when current is flowing therein. The readbit line 32 is galvanically connected to the MTJ element 2, e.g. bymeans of a connect layer 36 and a via 39, and is therefore electricallycouplable to the MTJ element 2. The two bit lines 32, 34 can only beseen in the top view as they run in parallel. All other elements of thememory cell 30 are as explained above for the prior art memory cell 1.

A matrix 38 of 4 of these MRAM cells 30, called cells A, B, C and D, isshown schematically in FIG. 8, or in a simplified block schematic inFIG. 9. A diagrammatic elevational view is shown in FIG. 10. It is to benoted that FIG. 8 to FIG. 11 concern a 2×2 array only. In reality thememory array 38 will generally be a lot larger. It is furthermore to benoted that the structure in FIG. 10 is partially inverted for claritypurposes: digit lines 4 physically run underneath the MTJ elements 2 (atthat side of the MTJ elements 2 oriented towards the substrate in whichthe transistor T is provided), and write bit lines 34 physically runover the MTJ elements 2 (at that side of the MTJ elements 2 orientedaway from the substrate in which the transistor T is provided). Read bitlines 32 are physically located adjacent write bit lines 34. However, ifdrawn that way, the read and write bit lines 32, 34 would obscure themagnetoresistive elements 2.

It can be seen in FIG. 8 and FIG. 10 that bit lines 32, 34 are commonfor all memory cells 30 in one column of the memory array 38, and thatdigit lines 4 and word lines 8 are common for all memory cells 30 in arow of the memory array 38. A word line 8 is connected to a switchingelement T in each cell, e.g. to a transistor switching element.

The space D1 between the read bit line 32 and the write bit line 34 ispreferably the minimum metal pitch of the manufacturing process in whichthe MRAM cells 30 are made, e.g. typically limited by lithography. Thewidth D2 of the read bit lines 32 is preferably as close as possible tothe minimum metal width of the manufacturing process with which the MRAMcells 30 are made, e.g. typically limited by lithography. It may besomewhat larger than this minimum width, however. The width D3 of thewrite bit lines 34 is preferably at least that width that substantiallycovers the MTJ element 2.

The distance D4 between the MTJ element 2 and the write bit line 34 issomewhat larger than in a conventional MRAM cell 1. It should, however,preferably be kept as small as possible. As an example, the distance D4can be equal or less than a regular oxide thickness between twosubsequent metallization layers.

When in the memory array 38, for example a cell A (see FIG. 8) needs tobe written and cell C needs to be read, the operation is as follows(with reference to FIG. 11):

Blocks 40, 42, 44, 46, 48 form together selecting circuitry. Through a“predecoders and logic” block 40, cell A is selected for write. Thismeans that the appropriate write bit line 34 is connected through a “bitline or column select” block 42 to a “write bit line current source” 44.The “precoders and logic” block 40 together with a “row select decoder”46 selects cell A also for write, which means that the appropriate digitline 4 is connected with a “digit line current source” 48. The word line8 of the cell to be written in is set to a value to turn off theassociated switching element T, e.g. in case of a transistor, forinstance, zero volt. In this way, current flows through both the writebit line 34 and the digit line 4 of the selected cell. Those currentstogether provide a magnetic field able to change the direction of themagnetic vector of the free layer 12 of the memory element 2, while thecurrent in either strip by itself is not able to change the storagestate. The current levels are designed to be much smaller than the fieldrequired to rotate the magnetization of the pinned layer 10. Theresistance of the MTJ cell 2 is brought in this way to a LoRes or HiRes(depending on the direction of the current through the bit line 34,which is dependent on the content to be stored in the memory cell 2).The relative resistance change between HiRes and LoRes depends on thevoltage applied to the bit line: it is about 25% at a bit line voltageof 0.6V, about 35% at a bit line voltage of 0.3V and about 45% at a bitline voltage of 0.1V.

The created magnetic field H is related to the write current I asfollows: H=I/6.28R, where H is the magnetic field at a radius R from thecenter of the field. The center of the field is the metal wire in whichthe current I flows.

The write current through the write bit line 34 is between 0.5 mA and 5mA. The write current in the MRAM cell 30 according to the presentinvention needs to be somewhat higher than in prior art devices, becausethe distance between line 34 and the magnetic layers of the memoryelement is slightly larger than when the prior art write bit line 6 wasattached to the memory element 2. The write current to be used dependson the size of the memory element 2 and on the technology used.

At the same moment of writing to cell A, cell C (FIG. 8) is selected forread. This means that the “bit line or column select” block 42 connectsthe read bit line 32 of cell C (which happens to be also the read bitline 32 of cell A in the example given) with the “sense amplifiers” 50.The “row select decoder” 46 applies to the word line 8 of the row onwhich cell C is located, a voltage suitable to turn the associatedswitching element T in the on-state. For example in case of a transistoras switching element T, the applied voltage can be Vdd. At that moment,the read bit line 32 is electrically coupled to the MTJ element 2. Thestate of the memory cell 30 is determined by measuring the resistance ofmemory element 2 when a sense current much smaller than the writecurrents (typically in the μA range), is passed perpendicularly throughthe memory element 2. The magnetic field of this sense or read currentis negligible and does not affect the magnetic state of the memory cell30. The probability of tunneling of charge carriers across the tunnelbarrier layer 14 depends on the relative alignment of the magneticmoments of the free layer 12 and the pinned layer 10. The tunnelingprobability of the charge carriers is highest, and thus the resistancelowest, when the magnetic moments of both layers are aligned. Thetunneling probability of the charge carriers is lowest, and thus theresistance highest, when the magnetic moments are anti-aligned. As aresult, the two possible magnetization directions of the free layeruniquely define two possible bit states (0 or 1) for the memory cell.

Cell A can thus be written, and cell C can be read at the same time,cell A and cell C being two cells on the same column of the array. Or,in other words, the matrix or array 38 described can be used in aread-while-write operation.

If cell A has to be written, and cell B has to be read, the write bitline 34 of cell A and the digit line 4 of cell A are connected to theirrespective current sources 44, 48. Furthermore, the read bit line 32 ofcell A is disabled by disconnecting it from the sense amplifiers 50. Forcell B, the write bit line 34 is disabled of course, but the read bitline 32 of cell B is connected to the sense amplifiers 50. Also the wordline 8 of the switching element, e.g. selecting transistor T of cell B(and automatically for cell A, but this does not have consequences) isapplied with a voltage which sets the switching element, e.g. selectingtransistor T in the on-state.

Now cell A can be written and cell B can be read at the same time, cellA and cell B being two cells on the same row of the array.

When a write operation is ongoing, a high current (mA range) in thewrite bit line 34 will induce a magnetic field. Through the read bitline 32, which is parallel to the write bit line 34, a small currentwill flow in the μA range, which is basically the current through theread MTJ and the switching element, e.g. the selecting transistor of theMRAM cell. This small current will cause only a small magnetic field,which does not influence the storage state of the MTJ. It is noted thatthis small magnetic field in the read bit line 32 is in distance fartheraway from the MTJ element 2 than the write bit line 34, which reducesthe effect of the small magnetic field on the MTJ element 2 evenfurther.

In principle, the speed of operation of the MRAM memory array 38 can bedoubled with regard to the speed of a prior art MRAM memories with onebit line because write and read operations on different cells can now bedone simultaneously. For example, in 0.6 μm technology, a write or readspeed of 18 ns can be reached. In future more advanced technologies,still higher read and write speeds will be possible.

As for the prior art devices, an MRAM memory according to the presentinvention can also be used for separate read and write operations byonly selecting one memory cell at a time. Read and write operations canalso be carried out at the same moment on different cells when they arelocated on different rows and columns.

It is to be understood that although specific constructions andconfigurations, as well as materials, have been discussed herein fordevices according to the present invention, deviations can be madetherein without departing from the spirit and scope of the presentinvention.

According to a further embodiment (not represented in the drawings), theswitching element T can also be connected between the read bit line 32and the memory element 2 (instead of between the memory element 2 andthe ground line 24). The switching element T can again be switched on oroff by means of a word line 8. The switching element T may be forexample a transistor, the word line 8 being connected to its gate. Inthis case, a memory element 2 is only electrically connected to the readbit line 32 at the moment of being read.

1. A matrix (38) with magnetoresistive memory cells arranged inlogically organized rows and columns, each memory cell including amagnetoresistive element (2), furthermore comprising means forsimultaneously reading from one cell in a column and writing to anothercell in a column, or means for simultaneous reading from one cell in arow and writing to another cell in the same row.
 2. A matrix (38)according to claim 1, wherein the means for simultaneously reading andwriting in a row or a column comprise a first column line (34) and asecond column line (32) for each column, the first column line (34)being a write bit line and the second column line (32) being a read bitline, the first column line (34) being a continuous conductive stripwhich is magnetically couplable to the magnetoresistive element (2) ofeach of the memory cells of the column, the second column line (32)being a continuous conductive strip which is electrically couplable toan electrode of each of the same magnetoresistive elements (2) of thememory cells of the column to which the first column line (34) ismagnetically couplable.
 3. A matrix (38) according to claim 2, whereineach row has a digit line (4) and a word line (8) and each cell has aswitching element (T) for connecting another electrode of themagnetoresistive element (2) to a voltage source (24), the digit line(4) being a continuous conductive strip which is magnetically couplableto the magnetoresistive element (2) of each of the memory cells of a rowand the word line (8) being a continuous strip electrically connected toeach of the switching elements (T) of a row.
 4. A matrix (38) accordingto claim 2, wherein a closest approach distance of the first column line(34) to the magnetoresistive element (2) of a cell is smaller than aclosest approach distance of the second column (32) line to the samemagnetoresistive element (2).
 5. A matrix (38) according to any of theprevious claims, wherein the magnetoresistive elements (2) comprise amagnetic tunnel junction (MTJ).
 6. A read-while-write MRAM memorycomprising a matrix (38) according to any of the previous claims andselecting circuitry for selecting a cell to be read and a cell to bewritten.
 7. A read-while-write MRAM memory according to claim 6, whereinthe selecting circuitry comprises a row select decoder (46) and a columnselect decoder (42).
 8. A read-while-write MRAM memory according toclaim 3, wherein the selecting circuitry is adapted to provideelectrical energy to the first and second column lines (34, 32), thedigit lines (4) and the word lines (8) for simultaneous reading of onecell in a column and writing to another cell in the same column orreading from one cell in a row and writing to another cell in the samerow.
 9. A read-while-write MRAM memory according to claim 8, wherein arow current source (48) is connected to the row select decoder (46) forproviding a selected digit line (4) with electrical energy.
 10. Aread-while-write MRAM memory according to claim 8, wherein a write bitline current source (44) is connected to the column select decoder (42)for providing a selected write bit line (34) with electrical energy. 11.A read-while-write MRAM memory according to claim 6, furthermorecomprising sense amplifiers (50) connectable to the second column lines(32).
 12. A method of operating a matrix (38) with magnetoresistivememory cells arranged in logically organized rows and columns, each cellincluding a magnetoresistive element (2), comprising simultaneouslyreading from one cell in a column and writing to another cell in thesame column or simultaneously reading from one cell in a row and writingof another cell in the same row.
 13. A method according to claim 12,furthermore comprising selecting one row for reading and another row forwriting or selecting one column for reading and another column forwriting.
 14. A method according to claim 13, wherein the selecting stepincludes providing electrical energy to a write bit line (34) which ismagnetically couplable to the magnetoresistive element (2) to bewritten, to a read bit line (32) which is electrically couplable to afirst electrode of the magnetoresistive element (2) to be read, to adigit line (4) which is magnetically couplable to the memory element (2)to be written and to a word line (8) which is electrically connected toa switching element (T) for connecting a second electrode of themagnetoresistive element (2) to be read to a voltage source (24).